1. Field of the Invention
The present invention relates to a computer which has a plurality of operation fields in one instruction word and which executes the operation fields in parallel.
2. Description of the Related Art
Heretofore, the instruction system of a computer is designed to execute one operation with one instruction word. It is typical that a sequence of instruction words are read serially word by word so that the functions corresponding to those instruction words may be sequentially performed one by one.
Recently, computers having an improved processing speed have been designed with an instruction system for executing a plurality of operation fields using one instruction word, those operation fields being executed in parallel. Such computers are generally called LIW (Long Instruction Word) type or VLIW (Very Long Instruction Word) type computers. This type of computer has a plurality of arithmetic and logic units to execute the plurality of operation fields in parallel, the system requiring a vast amount of circuits as a consequence. This computer cannot have an architecture of a single LSI chip. Rather it requires a plurality of LSI chips. In particular, when fast devices such as ECLs (Emitter Coupled Logic Circuits) are employed as LSI, the number of LSI chips is increased due to the low integration of the ECL. When a computer has a multi-LSI chip architecture, the transfer rate of signals between chips is slower than the transfer rate within a chip. It is therefore difficult to shorten the total cycle time of the computer.
Even when a computer can be constituted of a single LSI chip, this architecture still requires a vast amount of circuits. It is thus very difficult to design the layout of the individual circuits so as to reduce a signal delay as much as possible.
The aforementioned LIW type and VLIW type computers execute a plurality of operation fields at the same time. Those computers should thus be designed to be able to make multiple accesses to register files that are designated as operands of operations. This requires that multiple access ports be provided for the register files, which inevitably increases the area of the register files occupying an LSI chip. Further, a computer having a pipelining structure needs a circuit to allow the result of an operation to be passed to the upstream of the pipeline. This not only requires an additional area for the bypass circuit but also increases the signal delay time, making it difficult to shorten the processing time.
What is more, many signal lines will concentrate between a plurality of arithmetic logic units and one register file. It is difficult to divide a computer into a plurality of chips without sacrificing the cycle time. Even with a computer having a single-LSI chip architecture, it is difficult to design the layout of a vast amount of circuits in the chip efficiently.
To overcome the above shortcomings, a computer having a plurality of register files has been proposed. In this computer, a plurality of operation fields are associated one to one with a plurality of register files. This design reduces the required connecting lines between the arithmetic logic units and the register files. In addition, each operation field is independent from the other operation fields. This design can reduce the number of required arithmetic and logic units for a single register file, thus decreasing the number of access ports for the register files. Further, if the computer has a pipelining structure, the number of circuits to allow the results of operations to be passed to the upstream of the pipeline would be reduced. The number of lines connecting the register files and arithmetic and logic units is also reduced. It is therefore easy to divide the circuitry with a pair of an arithmetic unit and a register file taken as a unit.
As the computer has a plurality of register files, however, data should be transferred between the register files. If the register files are provided for the respective operation fields, the result of an operation in one operation field is stored in the associated register file. When another operation field needs to refer to the operation result, that operation result should be transferred to the register file which is associated with that operation field which requires the reference. This transfer is accomplished by a data transfer operation between the register files. As this data transfer operation is executed for a plurality of operation fields, the operation provided in whichever operation field should specify the register file associated with the mentioned another operation field. Accordingly, the information of the data transfer operation field should be transferred to the arithmetic and logic unit associated with that another operation field. The independence between the individual operation fields is therefore no longer maintained, making the aforementioned designing of a multi-chip computer difficult. Even with a computer having an architecture of a single LSI chip, it is difficult to efficiently design the layout of a vast amount of individual circuits in the chip.
A general explanation of a VLIW is given in Norman Jouppi, et al., "Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines," Proceedings of Third International Conference on Architectural Support for Programming Languages and Operating Systems, 1989. In other words, this document explains the advantages over an ordinary serial processor and the basic pipelining, though no detailed structures are illustrated.
Further, an example of a VLIW machine having a single register file is disclosed in Andrew Wolf, et al., A Variable Instruction Stream Extension to the VLIW Architecture," Proceedings of Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 1991. This prior art differs from the present invention in that it has only one register file.
Furthermore, a VLIW machine having a plurality of register files is disclosed in J. Dehnert, et al., "Overlapped Loop Support in the Cydra 5," Proceedings of Third International Conference on Architectural Support for Programming Languages and Operating Systems, 1989. This prior art differs from the present invention in that while the machine has a register file for each arithmetic and logic unit, it is designed so that each instruction field can access a register file associated with another arithmetic and logic unit.